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FAN4822
ZVS Average Current PFC Controller
Features
* Average current sensing, continuous boost, leading edge PFC for low total harmonic distortion and near unity power factor * Built-in ZVS switch control with fast response for high efficiency at high power levels * Average line voltage compensation with brownout control * Current fed gain modulator improves noise immunity and provides universal input operation * Overvoltage comparator eliminates output "runaway" due to load removal * UVLO, current limit, and soft-start * Precision 1.3% reference
General Description
The FAN4822 is a PFC controller designed specifically for high power applications. The controller contains all of the functions necessary to implement an average current boost PFC converter, along with a Zero Voltage Switch (ZVS) controller to reduce diode recovery and MOSFET turn-on losses. The average current boost PFC circuit provides high power factor (>98%) and low Total Harmonic Distortion (THD). Built-in safety features include undervoltage lockout, overvoltage protection, peak current limiting, and input voltage brownout protection. The ZVS control section drives an external ZVS MOSFET which, combined with a diode and inductor, soft switches the boost regulator. This technique reduces diode reverse recovery and MOSFET switching losses to reduce EMI and maximize efficiency.
Block Diagram
FB 14 2.5V IAC 4 VRMS 5 ISENSE 3 RTCT 6 VCCZ REF 13 REF
+
VEAO - + VEA
1
8
GND
2
IEAO OVP VCC VCCZ 13.5V 2.7V
+ - -
R+
+
FB IEA
+
12
GAIN MODULATOR R-
-
S I LIMIT -1V
+ -
Q
R PFC OUT 11 S R Q Q ZVS OUT 10 S R Q Q PWR GND 9
OSC
ZV SENSE 7
- -
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FAN4822
PRODUCT SPECIFICATION
Pin Configuration
FAN4822 14-Pin DIP (P14) VEAO IEAO ISENSE IAC VRMS RTCT ZV SENSE 1 2 3 4 5 6 7 14 13 12 11 10 9 8 FB REF VCC PFC OUT ZVS OUT PWR GND GND VEAO IEAO ISENSE IAC VRMS RTCT ZV SENSE N/C FAN4822 16-Pin SOIC (S16W) 1 2 3 4 5 6 7 8 TOP VIEW 16 15 14 13 12 11 10 9 FB REF VCC PFC OUT ZVS OUT PWR GND GND N/C
TOP VIEW
Pin Description (Pin numbers is parentheses are for 16-pin package)
Pin 1 (1) 2 (2) 3 (3) 4 (4) 5 (5) 6 (6) 7 (7) 8 (10) 9 (11) 10 (12) 11 (13) 12 (14) 13 (15) 14 (16) Name VEAO IEAO ISENSE IAC VRMS RTCT ZV SENSE GND PWR GND ZVS OUT PFC OUT VCC REF FB Function Transconductance voltage error amplifier output. Transconductance current error amplifier output. Current sense input to the PFC current limit comparator. PFC gain modulator reference input. Input for RMS line voltage compensation. Connection for oscillator frequency setting components. Input to the high speed zero voltage crossing comparator. Analog signal ground. Return for the PFC and ZVS driver outputs. ZVS MOSFET driver output. PFC MOSFET driver output. Shunt-regulated supply voltage. Buffered output for the internal 7.5V reference. Transconductance voltage error amplifier input.
Absolute Maximum Ratings
Absolute maximum ratings are those values beyond which the device could be permanently damaged. Absolute maximum ratings are stress ratings only and functional device operation is not implied. Parameter Shunt Regulator Current (ICC) Peak Driver Output Current Analog Inputs Junction Temperature Storage Temperature Range Lead Temperature (Soldering, 10 sec) Thermal Resistance (JA) Plastic DIP Plastic SOIC -65 -0.3 Min Max 55 500 7 150 150 150 80 110 Unit mA mA V C C C C/W C/W
2
REV. 1.0.1 8/10/01
PRODUCT SPECIFICATION
FAN4822
Operating Conditions
Temperature Range FAN4822IX Min. -40 Max. 85 Units C
Electrical Characteristics
Unless otherwise specified, RT = 52.3k, CT = 470pF, TA = Operating Temperature Range (Note 1) Parameter Voltage Error Amplifier Input Voltage Range Transconductance Open Loop Gain PSRR Output Low Output High Source Current Sink Current Current Error Amplifier Input Voltage Range Transconductance Input Offset Voltage Open Loop Gain PSRR Output Low Output High Source Current Sink Current OVP Comparator Threshold Voltage Hysteresis ISENSE Comparator Threshold Voltage Delay to Output ZV Sense Comparator Propagation Delay Threshold Voltage Input Capacitance 100mV Overdrive 7.35 7.5 6 50 7.65 ns V pF -0.8 -1.0 150 -1.15 300 V ns 2.6 80 2.7 120 2.8 150 V mV VIN = 0.5V, VOUT = 6V VIN = 0.5V, VOUT = 1.5V 6.0 -30 40 VCCZ - 3V < VCC < VCCZ - 0.5V 60 60 VNON-INV = VINV, IEAO = 3.75V -1.5 130 195 3 75 75 0.65 6.7 -80 80 1 2 310 15 V mV dB dB V V A A VIN = 0.5V, VOUT = 6V VIN = 0.5V, VOUT = 1.5V 6.0 -40 40 VCCZ - 3V < VCC < VCCZ - 0.5V VNON-INV = VINV, VEAO = 3.75V Feedback Reference Voltage VEAO = VFB 0 50 2.4 60 60 70 2.5 75 75 0.65 6.7 -80 80 1 7 120 2.6 V V dB dB V V A mA Conditions Min. Typ. Max. Units
REV. 1.0.1 8/10/01
3
FAN4822
PRODUCT SPECIFICATION
Electrical Characteristics (Continued)
Unless otherwise specified, RT = 52.3k, CT = 470pF, TA = Operating Temperature Range (Note 1) Parameter Gain Modulator Gain (Note 2) IIAC = 100mA, VVRMS = 0V, VFB = 0V IIAC = 50mA, VVRMS = 1.2V, VFB = 0V IIAC = 100A, VVRMS = 1.8V, VFB = 0V IIAC = 100A, VVRMS = 3.3V, VFB = 0V Bandwidth Output Voltage Oscillator Initial Accuracy Voltage Stability Temperature Stability Total Variation Ramp Valley to Peak Voltage Dead Time CT Discharge Current Reference Output Voltage Line Regulation Load Regulation Temperature Stability Total Variation Long Term Stability Short Circuit Current PFC Comparator Minimum Duty Cycle Maximum Duty Cycle MOSFET Driver Outputs Output Low Voltage IOUT = -20mA IOUT = -100mA IOUT = -10mA, VCC = 8V Output High Voltage Output Rise/Fall Time Undervoltage Lockout Threshold Voltage Hysteresis VCCZ - 0.9 2.4 VCCZ - 0.6 2.9 VCCZ - 0.2 3.45 V V IOUT = 20mA IOUT = 100mA CL = 1000pF 9.5 9 0.4 1.5 0.8 10.3 10.3 40 1.0 3.5 1.5 V V V V V ns VIEAO > 6.7V VIEAO < 1.2V 90 95 0 % % Line, load, and temperature Tj = 125C, 1000 hours VCC < VCCZ - 0.5V, VREF = 0V -15 7.35 5 -40 TA = 25C, IREF = 1mA VCCZ - 3V < VCC < VCCZ - 0.5V 1mA < IREF, < 20mA 7.4 7.5 2 2 0.4 7.65 25 -100 7.6 10 15 V mV mV % V mV mA 100 4.5 Line, temperature 72 2.5 300 7.5 450 9.5 TA = 25C VCCZ - 3V < VCC < VCCZ - 0.5V 74 80 1 2 89 87 kHz % % kHz V ns mA IIAC = 250A VFB = 0V, VVRMS = 1.15V, IIAC = 250A 0.72 0.36 1.20 0.55 0.14 0.51 1.72 0.78 0.20 10 0.8 0.9 0.66 2.24 1.01 0.26 MHz V Conditions Min. Typ. Max. Units
4
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PRODUCT SPECIFICATION
FAN4822
Electrical Characteristics (Continued)
Unless otherwise specified, RT = 52.3k, CT = 470pF, TA = Operating Temperature Range (Note 1) Parameter Supply Shunt Voltage (VCCZ) Load Regulation Total Variation Start-up Current Operating Current ICC =25mA 25mA < ICC < 55mA Load and temperature VCC < 12.3V VCC = VCCZ - 0.5V 12.4 0.7 22 12.8 13.5 150 14.2 300 14.6 1.1 28 V mV V mA mA Conditions Min. Typ. Max. Units
Notes 1. Limits are guaranteed by 100% testing, sampling, or correlation with worst-case test conditions. 2. Gain = K x 5.3 V; K = (IGAINMOD - IOFFSET) x IAC x (VEAO - 1.5)-1.
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FAN4822
PRODUCT SPECIFICATION
Functional Description
Switching losses of wide input voltage range PFC boost converters increase dramatically as power levels increase above 200 watts. The use of zero-voltage switching (ZVS) techniques improves the efficiency of high power PFCs by significantly reducing the turn-on losses of the boost MOSFET. ZVS is accomplished by using a second, smaller MOSFET, together with a storage element (inductor) to convert the turn-on losses of the boost MOSFET into useful output power. The basic function of the FAN4822 is to provide a power factor corrected, regulated DC bus voltage using continuous, average current-mode control. Like Micro Linear's family of PFC/PWM controllers, the FAN4822 employs leading-edge pulse width modulation to reduce system noise and permit frequency synchronization to a trailing edge PWM stage for the highest possible DC bus voltage bandwidth. For minimization of switching losses, circuitry has been incorporated to control the switching of the ZVS FET.
bined parasitic capacitance of D1 and Q1 (or optional ZVS capacitor CZVS). At t3, the voltage across Q1 is sufficiently low that the controller turns Q2 off and Q1 on. Q1 then behaves as an ordinary PFC switch, storing energy in the boost inductor L1. The energy stored in L2 is completely discharged into the boost capacitor via D2 during the Q1 offtime and the value of L2 must be selected for discontinuousmode operation.
Component Selection
Q1 Turn-Off
Theory of Operation
Figure 1 shows a simplified schematic of the output and control sections of a high power PFC circuit. Figure 2 shows the relationship of various waveforms in the circuit. Q1 functions as the main switching FET and Q2 provides the ZVS action. During each cycle, Q2 turns on before Q1, diverting the current in L1 away from D1 into L2. The current in L2 increases linearly until at t2 it equals the current through L1. When these currents are equal, L1 ceases discharging current and is now charged through L2 and Q2. At time t2, the drain voltage of Q1 begins to fall. The shape of the voltage waveform is sinusoidal due to the interaction of L2 and the comL1
Because the FAN4822 uses leading edge modulation, the PFC MOSFET (Q1) is always turned off at the end of each oscillator ramp cycle. For proper operation, the internal ZVS flip-flop must be reset every cycle during the oscillator discharge time. This is done by automatically resetting the ZVS comparator a short time after the drain voltage of the main Q has reached zero (refer to Figure 1 sense circuit). This sense circuit terminates the ZVS on time by sensing the main Q drain voltage reaching zero. It is then reset by way of a resistor pull-up to VCC (R6). The advantage of this circuit is that the ZVS comparator is not reset at the main Q turn off which occurs at the end of the clock cycle. This avoids the potential for improper reset of the internal ZVS flip-flop. Another concern is the proper operation of the ZVS comparator during discontinuous mode operation (DCM), which will occur at the cusps of the rectified AC waveform and at light loads. Due to the nature of the voltage seen at the drain of the main boost Q during DCM operation, the ZVS comparator can be fooled into forcing the ZVS Q on for the entire period. By adding a circuit which limits the maximum on time of the ZVS Q, this problem can be avoided. Q3 in Figure 1 provides this function.
D1
+ C1 VREF 13 VREF FAN4822 12 VCC Q1 R3 22k R5 220 R6 22k 7 C3 33pF C4 330pF R4 51k 8 GND R2 Q3 ZV SENSE PFC OUT 11 Q2 ZVS OUT 10 PWR GND 9 MAX ZVS ON TIME LIMIT CZVS(OPT) D2 R1 C2 L2
C5
Figure 1. Simplified PFC/ZVS Schematic.
6
REV. 1.0.1 8/10/01
PRODUCT SPECIFICATION Q1 Turn-On
FAN4822
The turn-on event consists of the time it takes for the current through L2 to ramp to the L1 current plus the resonant event of L2 and the ZVS capacitor. The total event should occur in a minimum of 350-450ns, but can be longer at the risk of increasing the total harmonic distortion. Setting these times equal should minimize conducted and radiated emissions.
t Q1 ( OFF ) = t IL2 + t RES = 400ns (1)
A. SYSTEM CLOCK (INTERNAL)
B. RTCT
Where IL2 is equal to IL1. The value of L2 is calculated to remain in discontinuousmode:
V BUS x V RMS ( MIN ) x t IL2 L2 = ---------------------------------------------------------------2 x P OUT
C. ZVS GATE (Q2)
(2)
The resonant event occurs in 1/4 of a full sinusoidal cycle. For example, when a 1/4 cycle occurs in 200ns, the frequency is 1.25MHz.
D. VDS (Q2)
1 1 f RES = ---------------------------------- = --------------------4 x t RES 2 L2 x C ZVS
(3)
Rearranging and solving for L2:
4 x t RES 2 L2 = -------------------------2 x C ZVS
E. PFC GATE (Q1)
(4)
The resonant capacitor (CZVS) value is found by setting equations 2 and 4 equal to each other and solving for CZVS.
4 x t RES 2 x 2 x P OUT C ZVS = ---------------------------------------------------------------------------2 x V BUS x V RMS ( MIN ) x t IL2
F. VDS (Q1)
(5)
Application
Figure 3 displays a typical application circuit for a 500W ZVS PFC supply. Full design details are covered in application note 33, FAN4822 Power Factor Correction With Zero Voltage Resonant Switching.
G. IL2
t1 t2
t3
Figure 2. Timing Diagrams
REV. 1.0.1 8/10/01
7
8
D1 400VDC B1 R12 453k 1% GBU6G Q1 FQA24N50 R3 10 D4 UF4005
+
F1 L1 420uH @ 10A n = 57 FESI6JT D2 D3 MUR460 MUR860 R8 93.1k 1% R9 93.1k 1% R20 93.1k 1% C3 1000pF 50V R11 2.37k 1% 400VDC RTN C21 0.1F 200V Q2 FQP6N50 R1 3.3k 3W R10 102k 1% L2 8.5m @ 14A
FAN4822
LINE 8AMP 250VAC R13 402k 1% R23 402k 1% R15 16.2k 1% C6 0.47F 16V D5 1N4747A R6 10k C2 470pF 1600V C1 330F 450V C4 0.1F 50V R4 10k D6 1N4747A R14 100k 1% R22 453k 1%
C14 0.47F 250VAC
NEUTRAL
R18 0.0732 5W 1% D13 1N5401 1 NC IN A 3 4 2 D7 1N5401 TC4427 NC OUT A VS RTN IN B VS OUT B 8 7 6 5 R2 10
C12 2.2nF 50V C7 0.68F 50V R17 220k C13 100pF 50V C11 68nF 50V
C9 1F 50V
C10 1F 50V
D10 UF4005 R19 10k VEAO IEAO ISENSE IAC VRMS ZVS OUT PWR GND GND RTCT ZV SENSE 10 9 8 PFC OUT 11 VCC 12 REF 13 FB 2 3 4 5 6 7 C18 33pF 50V Q3 2N7000 R26 22k C22 100pF 1 14
Figure 3. FAN4822 Schematic.
FAN4822
R21 39k 2W R5 39k 2W
R27 220
R16 8.25k 1%
R24 22k
C8 2.2F 50V
C5 1F 50V
R7 47 C15 1500F 25V C16 1F 50V
D11 EGP20A L1 n = 2.5
R25 51k
R29 10k
D9 1N5819 D8 1N5819 1N4148
C17 1F 50V
C19 330pF 50V
C20 2.2nF 50V
PRODUCT SPECIFICATION
REV. 1.0.1 8/10/01
D12 EGP20A
PRODUCT SPECIFICATION
FAN4822
Mechanical Dimensions inches (millimeters)
Package: P14 14-Pin PDIP 0.740 - 0.760 (18.79 - 19.31) 14 0.240 - 0.260 0.295 - 0.325 (6.09 - 6.61) (7.49 - 8.25)
PIN 1 ID
0.070 MIN (1.77 MIN) (4 PLACES)
1 0.050 - 0.065 0.100 BSC (1.27 - 1.65) (2.54 BSC) 0.015 MIN (0.38 MIN)
0.170 MAX (4.32 MAX)
0.125 MIN (3.18 MIN)
0.016 - 0.022 SEATING PLANE (0.40 - 0.56)
0 - 15
0.008 - 0.012 (0.20 - 0.31)
Package: S16W 16-Pin Wide SOIC
0.400 - 0.414 (10.16 - 10.52) 16
0.291 - 0.301 0.398 - 0.412 (7.39 - 7.65) (10.11 - 10.47) PIN 1 ID
1 0.024 - 0.034 (0.61 - 0.86) (4 PLACES) 0.050 BSC (1.27 BSC) 0.095 - 0.107 (2.41 - 2.72) 0 - 8
0.090 - 0.094 (2.28 - 2.39)
0.012 - 0.020 (0.30 - 0.51)
SEATING PLANE 0.005 - 0.013 (0.13 - 0.33)
0.022 - 0.042 (0.56 - 1.07)
0.009 - 0.013 (0.22 - 0.33)
REV. 1.0.1 8/10/01
9
FAN4822
PRODUCT SPECIFICATION
Ordering Information
Part Number FAN4822IN FAN4822IM PFC/PWM Frequency -40C to 85C -40C to 85C Package 14-Pin PDIP (P14) 16-Pin Wide SOIC (S16W)
DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user.
www.fairchildsemi.com 8/10/01 0.0m 003 Stock#DS30004803 2001 Fairchild Semiconductor Corporation
2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.

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